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Additional info for An Introduction to Digital Techniques: Logic gates, Flip-flops, Counters and Shift registers
In practice; 'Low input activated FLIP-FLOPS' are used but the principle remains the same. R QI-o---- 0---- Fig. 30 Internal configuration of a high input activated R-S FLIP-FLOP. 6 q From R selecto~ switches of: 44 Channel 1. FLIP-FLOP Channel 1 switch or touchpad. 32 The clocked R-S FLIP-FLOP circuit symbol. Fig. 34 Circuit operation. Frequently, it is desirable to set up the input conditions, but delay the actual Setting or Resetting action until a pulse is received from another source. This pulse is called the ~CLOCK' pulse.
54. Two FLIP-FLOPS are used. They are called MASTER and Slave FLIP-FLOPS. The package is known, as a MASTER SLA VE D TYPE FLIP-FLOP. Both 'Master' and 'Slave' FLIP-FLOPS require a 'high' on their ck inputs to transferthe data from their d input, to their q output. The clock pulse on the CK input is fed directly to the 'Master' and is inverted to feed the 'Slave'. When the CK input is 'low' (prior to a clock pulse); the 'Master' is inhibited; data on its d input cannot enter; the 'Slave' receives a 'high' and is enabled; whatever is on the 'Master q' output (entered on the previous clock pulse) is passed to the 'Slave' q output.
R Input 5 H L L H L H H L H H L L H H H H H H But when both go Low. 35 The 'D'type FLIP-FLOP circuit symbol. 35. The D type FLIP-FLOP is a variation of the clocked R-S FLIP-FLOP. It has one input, the D (Data) input. It also eliminates the undetermined state present in the R-S and the clocked R-S FLIP-FLOP. Any data on the D input wi II have no effect on the a outputs until the CK input is taken 'high'. Fig. 37 Circuit operation. 36) CK If the CK input is 'low', any signal applied to the D input will have no effect on a or Q.