By Ali Hurson
Этот свежий сборник знакомит с последними достижениями в архитектуре компьютеров.
Register-Level communique in Speculative Chip Multiprocessors
Survey on procedure I/O Transactions and impression on Latency, Throughput, and different Factors
Hardware and alertness Profiling Tools
Model Transformation utilizing Multiobjective Optimization
Manual Parallelization as opposed to cutting-edge Parallelization ideas: The SPEC CPU2006 as a Case examine
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Additional resources for Advances in Computers, Volume 92
SM predicts the register dependencies for each new speculative thread relative to the predecessor thread in the control flow and the values that will flow through those dependencies. The data dependence constraints among instructions in Trace are alleviated with the use of the value prediction for live-ins of traces. Atlas uses AMA (atlas multiadaptive) predictor , a more aggressive correlated value prediction than SM and Trace, to avoid broadcasting and snooping of the register values. The thread identification based on loop iterations (as in SM) or on instruction traces (as in Trace) provides a good control and data predictability, but they experience severe load imbalance and coverage problems.
In MP98 (Merlot) and MAJC) saves the bandwidth in extremely small multiprocessor designs like CMPs, it imposes complex wiring, increases in number of read and write ports, and affects the cycle time and latencies. Hence, most of speculative CMP designs exploit distributed register structures to alleviate aforementioned issues noticed in designs with a shared register file organization. 2 Support for Register Communication The hardware support for register value communication in Multiscalar, Multiplex, and NEKO requires additional register storage banks and sets of bit masks per each core, which results in complex core designs.
The protocol mechanism for loop-live registers works as follows: 1. Read hit. If a speculative or nonspeculative thread issues a read request for a register in a valid state (VU, VS, or LC), the request is satisfied locally and that register remains in the same state. 2. Read miss. A read request for a register in the INV state causes the read miss and initiates BusR transaction. The read request for this register is issued on the bus along with the mask code of its speculative thread. Consequently, read miss incurs a consumer-initiated interthread communication.